About the Benefits of Intermediate VHDL Semantics for Correct Transformational Synthesis*

A design step transforms a specification into an implementation and may take place on several levels of abstraction. If we want to formally capture the design step in order to reason about its correctness we need on the one hand formal VHDL semantics capturing the static and dynamic aspects of the VHDL simulation model. On the other hand, we need special purpose semantics supporting the use of VHDL in a specific step of the design flow in a proper way. There is a gap between semantics of the first kind and of the latter kind. Therefore, we suggest to use intermediate semantics, which are versions of VHDL simulation semantics but more suited to be mapped to the dedicated semantics used as the basis for verifying correctness properties of synthesis steps.